1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a step of flattening a silicon oxide layer formed on a projected or depressed surface of a semiconductor device.
2. Description of the Related Art
A conventional semiconductor device-manufacturing method includes a step of forming a projected structure and a depressed structure on a silicon substrate. The projected structure is, for example, an electrode, a capacitor, a wiring layer, or the like, while the depressed structure is, for example, a trench, a contact hole, or the like. A silicon oxide (SiO.sub.2) layer is formed over the projected and depressed structures. In general, an "etch back" process and a "re-flow" process are used for flattening the silicon oxide layer, but these processes cannot completely flatten the silicon oxide layer. Since projected or depressed portions remain on the silicon oxide layer, the subsequent steps have to be carried out under various restrictions.
FIG. 1 and FIG. 2 are cross sectional views showing one conventional semiconductor device-manufacturing method. Referring to these FIGURES, first to fourth electrodes 2 to 5 are formed on a silicon substrate 1, and then a silicon oxide layer 6 is deposited over the electrodes 2 to 5 and silicon substrate 1. Subsequently, resist 7 is coated on the silicon oxide layer 6 by spin coating. This resist coating 7 has different thicknesses, depending upon the locations. To be specific, of the portions of the resist coating 7, the portion located above the region between the third and fourth electrodes 4 and 5 and the portion located above the fourth electrode 5 are inevitably thinner than the portions located above the first to third electrodes 2 to 4. In other words, the resist coating 7 is thin at portions located above the region between distantly-arranged electrodes and at portions located above wide electrodes, and is thick at portions located above the region between closely-arranged electrodes and at portions located above narrow electrodes.
Thereafter, the resist coating 7 and the silicon oxide layer 6 are etched back so as to flatten the silicon oxide layer 6. As a result, the silicon oxide layer 6 has different thicknesses, depending upon the locations. To be specific, of the portions of the silicon oxide layer 6, the portion located above the region between the third and fourth electrodes 4 and 5 and the portion located above the fourth electrode 5 become thinner than the portions located above the first to third electrodes 2 to 4. In other words, after the "etch back" process, the silicon oxide layer 6 becomes thick at portions overlaid with a thick resist coating, and becomes thin at portions overlaid with a thin resist coating. Therefore, the silicon oxide layer 6 has projected and depressed portions even after it is flattened in the "etch back" process.
FIGS. 3 and 4 are cross sectional views showing another conventional semiconductor device-manufacturing method. Referring to these FIGURES, first to fourth electrodes 12 to 15 are formed on a silicon substrate 11, and then a BPSG (boron phosphorous silicon glass) layer 16 is deposited over the electrodes 12 to 15 and silicon substrate 11.
Subsequently, the BPSG layer 16 is heated to re-flow, as shown in FIG. 4, so as to flatten the BPSG layer 16. The result of this "re-flow" process is similar to that of the "etch back" process mentioned above. That is, after the "re-flow" process, the BPSG layer 16 is thin at portions located above the region between distantly-arranged electrodes and at portions located above wide electrodes, and is thick at portions located above the region between closely-arranged electrodes and at portions located above narrow electrodes. Therefore, the BPSG layer 16 has projected and depressed portions even after it is flattened in the "re-flow" process.
A recently-developed submicron device has a high degree of integration. In this type of device, the central and peripheral portions of a semiconductor chip are greatly different in level, and the pitch of wiring layers is very short. An insulation layer of the sub-micron device has projected and depressed portions even after it is flattened in either the "etch back" process or "re-flow" process mentioned above, and the projected and depressed portions become a serious problem when a wiring layer and other structural elements are formed on the insulation layer. For example, if a wiring layer is formed on the projected and depressed portions of the insulation layer by deposition, accurate focusing is not ensured at the time of an exposure operation for patterning that wiring layer. As a result, the wiring layer is not patterned accurately, and the sections into which it is patterned have shapes deviating from the intended shapes. Consequently, the resultant semiconductor device does not have reliable electrical characteristics; it may have defects, such as open wiring layer sections.